MohammadParsa
RostamzadehKhameneh

Professional Summary

Computer Engineering M.Sc. student (Embedded Systems) and graduate research assistant in the Computer Engineering Group at Paderborn University. Builds approximate-computing tools for FPGA-based DNN accelerators: RTL-level approximation, design-space exploration, and large-scale synthesis and simulation on an HPC cluster. Co-author of an ARC 2026 paper (Springer LNCS), with a second paper under review. Software engineering background in Python, C/C++ and C#.

Professional Experience

Graduate Research Assistant (Wissenschaftliche Hilfskraft)

Computer Engineering Group (Prof. Dr. Marco Platzner), Paderborn University2025 – Present
  • Co-developed CLAS, a cross-layer approximate synthesis framework for LUT-based DNN accelerators on FPGAs. It achieved an additional 33% area savings over algorithmic-level approximation baselines with a 4% accuracy drop on MNIST (ARC 2026).
  • Co-developed a partition-based design-space exploration framework for approximate accelerators, combining spectral graph partitioning with sensitivity-driven error-budget allocation. It speeds up exploration by up to 92.9× while meeting every error constraint across 4 kernels and 20 size configurations (under review).
  • Extended CIRCA, the group’s approximate circuit generation framework, with evolutionary approximation variants (Python, C, Yosys, ABC).
  • Automated parallel synthesis and simulation campaigns on the Noctua 2 HPC cluster (PC2) using SLURM.

Software Developer (Intern)

Hesab Rayan Pars2024 – 2025
  • Developed an accounting web application with C# and ASP.NET.

Publications

  1. ARC 2026

    CLAS: A Cross-Layer Approximate Synthesis Framework for LUT-based DNN Accelerators

    A. Jafari, A. H. Hadipour, M. Awais, M. Rostamzadeh-Khameneh, H. Ghasemzadeh Mohammadi, M. Platzner

    22nd International Symposium on Applied Reconfigurable Computing (ARC) · Springer LNCS · Cagliari, Italy

  2. DATE 2027Under review

    Divide et Approxima: Scalable Design Space Exploration for Approximate Accelerators via Partitioning and Sensitivity-driven Error Allocation

    Submitted to Design, Automation and Test in Europe Conference (DATE)

Education

M.Sc. in Computer Engineering

Paderborn University2024 – Present

Specialized in Embedded Systems

  • VLSI design: hands-on standard-cell design in Cadence Innovus.

B.Sc. in Computer Engineering

Tehran Azad University2018 – 2023

Specialized in Software Development